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Your search returned 26 records. Click on the hyperlinks to view further details of Titles.. |
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Magazine Name : Ieee Journal Of Solid-State Circuits
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Year : 2003 Volume number : 38 Issue: 11 |
Self-Biased High-Bandwidth Low-Jitter 1-To-4096 Multiplier Clock Generator Pll
(Article)
Subject:
Analog Circuits
,
Phase-Looked Loop(Pll)
,
Self-Biased
Author:
John G
Maneatis
Jaeha
Kim
Jay
Maxey
page:
1795
-
1803
A Low-Power Adaptive Bandwidth Pll And Clock Buffer With Supply-Noise Compensation
(Article)
Subject:
Adaptive Bandwidth Pll
,
Low-Power Analog Circuits
,
Timing Jitter
Author:
Mozhgan
Mansuri
Chih-Kong Ken
Yang
page:
1804
-
1812
A 10-Ghz Global Clock Distribution Using Coupled Standing-Wave Oscillators
(Article)
Subject:
Clock Distribution
,
Standing Wave
,
Coupled Oscillators
Author:
Frank O
Mahony
C. Patrick
Yue
S Simon
Wong
page:
1813
-
1820
A 2.5-10-Gb/S Cmos Transceiver With Alternating Edge-Sampling Phase Detection For Loop Characteristic Stabilization
(Article)
Subject:
Clock And Data Recovery
,
Variable Jitter Condition
,
Phase Detector Gain
Author:
Moon-Sang
Hwang
Deog-Kyoon
Jeong
Bong-Joon
Lee
page:
1821
-
1829
40-Gb/S 2:1 Multiplexer And 1:2 Demultiplexer In 120-Nm Standerd Cmos
(Article)
Subject:
Cmos
,
Demultiplexer
,
Multiplexer
Author:
Daniel
Kehrer
Martin
Wurzer
Arpad L
Scholtz
page:
1830
-
1837
Dynamic Sleep Transistor And Body Bias For Active Leakage Power Control Of Microprocessors
(Article)
Subject:
Body Bias
,
Low Power
,
Mtcmos
Author:
James W.
Tschanz
Siva G
Narendra
Vivek
De
page:
1838
-
1845
A 400-Mt/S 6.4-Gb/S Multiprocessor Bus Interface
(Article)
Subject:
Dll
,
Edge Rate
,
Processor
Author:
Harry
Muljono
Mitsuhiro
Adachi
Stefan
Rusu
page:
1846
-
1856
A 2 X Load/Store Pipe For A Low-Power 1-Ghz Embedded Processor
(Article)
Subject:
Low Power
,
Cache Memories
,
Microprocessor
Author:
Zongjian
Chen
Daniel
Murray
Mark
Pearce
page:
1857
-
1865
A Tcp Offload Accelerator For 10gb/S Ethernet In 90-Nm Cmos
(Article)
Subject:
Tcp
,
Gigabit Ethernet
,
Offload
Author:
Yatin
Hoskote
David
Finan
Nitin
Borkar
page:
1866
-
1875
A Vliw Processor With Reconfigurable Instruction Set For Embedded Applications
(Article)
Subject:
Pipeline
,
Energy Consumption
,
Reconfigurable Processor
Author:
Andrea
Lodi
Mario
Toma
Andrea
Cappelli
page:
1876
-
1886
A 1.5-Ghz 130-Nm Itanium 2 Processor With 6-Mb On-Die L3 Cache
(Article)
Subject:
Circuit Design
,
Microprocessor
,
Computer Architecture
Author:
Stefan
Rusu
Simon
Tam
Harry
Muljono
page:
1887
-
1895
A 1.3-Ghz Fifth-Generation Sparc64 Microprocessor
(Article)
Subject:
Microprocessors
,
Clock Distribution
,
Computer Architecture
Author:
Hisashige
Ando
Yuuji
Yoshida
Seishi
Okada
page:
1896
-
1905
A 0.24-Um 2.0-V 1t1mtj 16-Kb Nonvolatile Magnetoresistance Ram With Self-Reference Sensing Scheme
(Article)
Subject:
Mram
,
0.24-Um Technology
,
Self-Reference Sensing Scheme
Author:
Gitae
Jeong
Wooyoung
Cho
Kinam
Kim
page:
1906
-
1910
A 32-Mb Chain Feram With Segment/Stitch Array Architecture
(Article)
Subject:
Ferroelectric Memory
,
Nonvolatile Memory
,
Random Access Memory (Ram)
Author:
Thomas
Roehr
Michael
Jacob
Gerhard
Beitel
page:
1911
-
1919
512-Mb Prom With A Three-Dimensional Array Diode/Antifuse Memory Cells
(Article)
Subject:
Nonvolatile Memory
,
Antifuse
,
Cmos Memory
Author:
Mark
Johnson
Ali Al
-Shamma
Thomas
Lee
page:
1920
-
1928
A 1.8-V 128-Mb 125-Mhz Multilevel Cell Flash Memory With Flexible Read While Write
(Article)
Subject:
Flash
,
Amplifier
,
Nonvolatile Memory
Author:
Daniel
Elmhurst
Matthew
Goldman
page:
1929
-
1933
A 90-Nm Cmos 1.8-V 2-Gb Nand Flash Memory For Mass Storage Applications
(Article)
Subject:
Cmos Memory Integrated Circuits
,
Flash Memory
,
Nand Flash Memory
Author:
June
Lee
Jong-Sik
Lee
Kang-Deog
Suh
page:
1934
-
1942
A 1.2-V 1.5-Gb/S 72-Mb Ddr3 Sram
(Article)
Subject:
72 Mb
,
1.5 Gb/S
,
Cmos Memory Circuits
Author:
Uk-Rae
Cho
Yong-Jin
Yoon
Kee-Sik
Ahn
page:
1943
-
1951
16.7-Fa/Cell Tunnel-Leakage-Suppressed 16-Mb Sram For Handling Cosmic-Ray-Induced Multierrors
(Article)
Subject:
Sram
,
Cosmic Ray
,
Low Standby Current
Author:
Kenichi
Osada
Yoshikazu
Saitoh
Eishi
Ibe
page:
1952
-
1957
A Mismatch-Dependent Power Allocation Technique For Match-Line Sensing In Content-Addressable Memories
(Article)
Subject:
Low Power
,
High Speed
,
Associative Memory
Author:
Igor
Arsovski
Ali
Sheikholeslami
page:
1958
-
1966
An Embedded Dram With A 143-Mhz Sram Interface Using A Sense-Synchronized Read/Write
(Article)
Subject:
Cmos Memory Integrated Circuits
,
System-On-Chip
,
Embedded Dram
Author:
Yasuhiko
Taito
Kazutami
Arimoto
Futoshi
Igaue
page:
1967
-
1973
A 5.6-Ns Random Cycle 144-Mb Dram With 1.4 Gb/S/Pin And Ddr3-Sram Interface
(Article)
Subject:
Memory
,
Cache Memory
,
Embedded Dram
Author:
Darren
Anand
John
Barth
Harold
Pilo
page:
1974
-
1980
A Fully Integrated 0.13-Um Cmos Mixed-Signal Soc For Dvd Player Applications
(Article)
Subject:
Cmos
,
Dvd
,
Read Channel
Author:
Koji
Okamoto
Takashi
Morie
Kouichi
Nagano
page:
1981
-
1991
A 51.2-Gops Scalable Video Recognition Processor For Intelligent Cruise Control Based On A Linear Array Of 128 Four-Way Vliw Processing Elements
(Article)
Subject:
Image Processing
,
Parallel Architecture
,
Parallel Processor
Author:
Shorin
Kyo
Takuya
Koga
Ichiro
Kuroda
page:
1992
-
2000
A Single-Chip 802.11a Mac/Phy With A 32-B Risc Processor
(Article)
Subject:
Signal Processing
,
Wireless Lan
,
Adaptive Equalizers
Author:
Koji
Tsuchie
Toshitada
Saito
Tetsuya
Fujita
page:
2001
-
2009
A 13.3-Mb/S 0.35-Um Cmos Analog Turbo Decoder Ic With A Configurable Interleaver
(Article)
Subject:
Analog Decoding
,
Turbo Codes.
,
Iterative Decoding
Author:
Vincent C
Gaudet
P. Glenn
Gulak
page:
2010
-
2015
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